Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version3247384
date_generatedMon Nov 29 08:22:46 2021 os_platformWIN64
product_versionVivado v2021.1 (64-bit) project_ide0eb885220eb4ab7b3a616fbd98d4505
project_iteration1 random_id90f29b6280c45b589ae414ec896ac89c
registration_id210643289_0_0_752 route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-8400 CPU @ 2.80GHz cpu_speed2808 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram17.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_apply=2 basedialog_ok=9 basedialog_yes=3 constraintschooserpanel_add_files=1
expruntreepanel_exp_run_tree_table=1 filesetpanel_file_set_panel_tree=30 flownavigatortreepanel_flow_navigator_tree=3 fpgachooser_category=1
fpgachooser_family=1 fpgachooser_fpga_table=2 fpgachooser_package=2 fpgachooser_speed=2
hjfilechooserrecentlistpreview_recent_directories=2 hpopuptitle_close=1 mainmenumgr_edit=2 mainmenumgr_file=4
mainmenumgr_project=2 mainmenumgr_reports=2 mainmenumgr_tools=4 mainmenumgr_view=2
mainwinmenumgr_layout=2 newprojectwizard_do_not_specify_sources_at_this_time=1 pacommandnames_add_sources=1 pacommandnames_auto_update_hier=2
pacommandnames_new_project=1 projectnamechooser_project_name=1 rdicommands_custom_commands=2 rdicommands_settings=4
saveprojectutils_save=1 settingsprojectgeneralpage_choose_device_for_your_project=1 settingsprojectgeneralpage_target_language=1 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
srcmenu_ip_hierarchy=2 srcmenu_open_selected_source_files=1 syntheticagettingstartedview_recent_projects=1
java_command_handlers
addsources=2 exitapp=1 newproject=1 runbitgen=3
showview=2 toolssettings=4
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bscane2=1 bufg=2 carry4=10 fdre=124
gnd=15 ibuf=1 lut2=1 lut3=2
lut4=6 lut5=52 lut6=98 obuf=8
ramb18e1=1 ramd32=24 ramd64e=8 rams32=8
vcc=3
pre_unisim_transformation
bscane2=1 bufg=2 carry4=10 fdre=124
gnd=15 ibuf=1 lut2=1 lut3=2
lut4=6 lut5=2 lut6=48 lut6_2=50
obuf=8 ram32m=4 ram64m=2 ramb18e1=1
vcc=3

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=124 srls_augmented=0
srls_newly_gated=0 srls_total=0

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clocks=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=default::[not_specified] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=default::[not_specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_congestion_level=default::5 -min_level=default::[not_specified] -name=default::[not_specified]
-no_header=default::[not_specified] -of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=[specified]
-quiet=default::[not_specified] -return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified]
-routes=default::[not_specified] -setup=default::[not_specified] -show_all_congestion_windows=default::false -suggestion=default::[not_specified]
-timing=default::[not_specified] -verbose=default::[not_specified]
usage
runtime=0.034 secs
usage_count
qor_summary=4

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -merge_exceptions =default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified]
-return_string=default::[not_specified] -slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-17=38 timing-18=8

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.000215 clocks=0.000909
confidence_level_clock_activity=Medium confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=High confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.097107 die=xc7a100tcsg324-1 dsp_output_toggle=12.500000 dynamic=0.003118
effective_thetaja=4.56 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.000064 input_toggle=12.500000
junction_temp=25.5 (C) logic=0.000979 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.100226 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=csg324 pct_clock_constrained=1.000000 pct_inputs_defined=100 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.000952 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=5.7 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.56
user_junc_temp=25.5 (C) user_thetajb=5.7 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000000
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.018140 vccaux_total_current=0.018140 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000016
vccbram_static_current=0.000256 vccbram_total_current=0.000272 vccbram_voltage=1.000000 vccint_dynamic_current=0.003102
vccint_static_current=0.014999 vccint_total_current=0.018102 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000000
vcco33_static_current=0.004000 vcco33_total_current=0.004000 vcco33_voltage=3.300000 version=2021.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_prohibited=0 bufgctrl_used=2
bufgctrl_util_percentage=6.25 bufhce_available=96 bufhce_fixed=0 bufhce_prohibited=0
bufhce_used=0 bufhce_util_percentage=0.00 bufio_available=24 bufio_fixed=0
bufio_prohibited=0 bufio_used=0 bufio_util_percentage=0.00 bufmrce_available=12
bufmrce_fixed=0 bufmrce_prohibited=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_prohibited=0 bufr_used=0
bufr_util_percentage=0.00 mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_prohibited=0
mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00 plle2_adv_available=6 plle2_adv_fixed=0
plle2_adv_prohibited=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_prohibited=0 dsps_used=0
dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_prohibited=0 block_ram_tile_used=0.5
block_ram_tile_util_percentage=0.37 ramb18_available=270 ramb18_fixed=0 ramb18_prohibited=0
ramb18_used=1 ramb18_util_percentage=0.37 ramb18e1_only_used=1 ramb36_fifo_available=135
ramb36_fifo_fixed=0 ramb36_fifo_prohibited=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bscane2_functional_category=Others bscane2_used=1 bufg_functional_category=Clock bufg_used=2
carry4_functional_category=CarryLogic carry4_used=10 fdre_functional_category=Flop & Latch fdre_used=124
ibuf_functional_category=IO ibuf_used=1 lut2_functional_category=LUT lut2_used=1
lut3_functional_category=LUT lut3_used=3 lut4_functional_category=LUT lut4_used=7
lut5_functional_category=LUT lut5_used=57 lut6_functional_category=LUT lut6_used=81
obuf_functional_category=IO obuf_used=8 ramb18e1_functional_category=Block Memory ramb18e1_used=1
ramd32_functional_category=Distributed Memory ramd32_used=24 ramd64e_functional_category=Distributed Memory ramd64e_used=8
rams32_functional_category=Distributed Memory rams32_used=8
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_prohibited=0 f7_muxes_used=0
f7_muxes_util_percentage=0.00 f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_prohibited=0
f8_muxes_used=0 f8_muxes_util_percentage=0.00 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_prohibited=0 lut_as_logic_used=105
lut_as_logic_util_percentage=0.17 lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_prohibited=0
lut_as_memory_used=24 lut_as_memory_util_percentage=0.13 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_prohibited=0 register_as_flip_flop_used=124
register_as_flip_flop_util_percentage=0.10 register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_prohibited=0
register_as_latch_used=0 register_as_latch_util_percentage=0.00 slice_luts_available=63400 slice_luts_fixed=0
slice_luts_prohibited=0 slice_luts_used=129 slice_luts_util_percentage=0.20 slice_registers_available=126800
slice_registers_fixed=0 slice_registers_prohibited=0 slice_registers_used=124 slice_registers_util_percentage=0.10
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_prohibited=0 lut_as_logic_used=105 lut_as_logic_util_percentage=0.17 lut_as_memory_available=19000
lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=24 lut_as_memory_util_percentage=0.13
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_in_front_of_the_register_is_unused_available=0 lut_in_front_of_the_register_is_unused_fixed=0
lut_in_front_of_the_register_is_unused_prohibited=0 lut_in_front_of_the_register_is_unused_used=14 lut_in_front_of_the_register_is_used_available=14 lut_in_front_of_the_register_is_used_fixed=14
lut_in_front_of_the_register_is_used_prohibited=14 lut_in_front_of_the_register_is_used_used=8 register_driven_from_outside_the_slice_fixed=8 register_driven_from_outside_the_slice_used=22
register_driven_from_within_the_slice_fixed=22 register_driven_from_within_the_slice_used=102 slice_available=15850 slice_fixed=0
slice_prohibited=0 slice_registers_available=126800 slice_registers_fixed=0 slice_registers_prohibited=0
slice_registers_used=124 slice_registers_util_percentage=0.10 slice_used=42 slice_util_percentage=0.26
slicel_fixed=0 slicel_used=27 slicem_fixed=0 slicem_used=15
unique_control_sets_available=15850 unique_control_sets_fixed=15850 unique_control_sets_prohibited=0 unique_control_sets_used=14
unique_control_sets_util_percentage=0.09 using_o5_and_o6_available=0.09 using_o5_and_o6_fixed=0.09 using_o5_and_o6_prohibited=0.09
using_o5_and_o6_used=16 using_o5_output_only_available=16 using_o5_output_only_fixed=16 using_o5_output_only_prohibited=16
using_o5_output_only_used=0 using_o6_output_only_available=0 using_o6_output_only_fixed=0 using_o6_output_only_prohibited=0
using_o6_output_only_used=8
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_prohibited=0 bscane2_used=1
bscane2_util_percentage=25.00 capturee2_available=1 capturee2_fixed=0 capturee2_prohibited=0
capturee2_used=0 capturee2_util_percentage=0.00 dna_port_available=1 dna_port_fixed=0
dna_port_prohibited=0 dna_port_used=0 dna_port_util_percentage=0.00 efuse_usr_available=1
efuse_usr_fixed=0 efuse_usr_prohibited=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_prohibited=0 frame_ecce2_used=0
frame_ecce2_util_percentage=0.00 icape2_available=2 icape2_fixed=0 icape2_prohibited=0
icape2_used=0 icape2_util_percentage=0.00 pcie_2_1_available=1 pcie_2_1_fixed=0
pcie_2_1_prohibited=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00 startupe2_available=1
startupe2_fixed=0 startupe2_prohibited=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_prohibited=0 xadc_used=0
xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -incremental=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified]
-max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1
-max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified]
-no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7a100tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=topmodule -verilog_define=default::[not_specified]
usage
elapsed=00:00:27s hls_ip=0 memory_gain=0.000MB memory_peak=1122.230MB