| Good | C | To be completed | |
| Needs a task | A | Automatic translation. To check and correct | |
| obsolete or partial | X | Not useful, does not exist | |
| Non-existent or very obsolete | V | Text to be verified | |
| _* | moved | ||
| not verified |
| Act | Title | EN | FR | DE | PT | RU | EL | ES | IT | NL | To do | |||
| Logisim References | ||||||||||||||
| 3.5 | About the program | __ | __ | _A | __ | __ | ||||||||
| 3.5 | GNU General Public License v3 | __ | X | X | X | X | ||||||||
| 3.5 | GNU General Public License v3, translated | X | __ | __ | *T | __ | ||||||||
| 3.5 | The Logisim-evolution user’s Guide | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Beginner's tutorial | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Step 0: Orienting yourself | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Step 1: Adding gates | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Step 2: Adding wires | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Step 3: Adding text | __ | __ | _A | __ | _A | ||||||||
| 3.5 | Step 4: Testing your circuit | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Step 5: The step by step mode | _V | __ | _A | _A | _A | ||||||||
| 3.5 | The graphical interface | __ | __ | __ | _V | _V | ||||||||
| 3.5 | The canvas | _V | __ | __ | __ | _A | ||||||||
| 3.5 | The menus | _V | __ | _A | __ | _A | ||||||||
| 3.5 | The explorer pane | _V | __ | _V | _V | _V | ||||||||
| 3.5 | The tools bars | _V | __ | __ | __ | __ | ||||||||
| 3.5 | The attribute table | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Attributes of tools and components | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Subcircuits | __ | __ | _A | _V | _V | ||||||||
| 3.5 | Creating circuits | __ | __ | _A | _V | _V | ||||||||
| 3.5 | Using subcircuits | _V | __ | _A | _V | _V | ||||||||
| 3.5 | Selecting the appearance of a subcircuit | _V | __ | _A | _A | _A | ||||||||
| 3.5 | Personalise appearance | _V | __ | _A | _A | _A | ||||||||
| 3.5 | Debugging subcircuits | __ | __ | _A | _V | _V | ||||||||
| 3.5 | Logisim libraries | __ | __ | _A | __ | __ | ||||||||
| 3.5 | Additional features | _V | __ | _V | _V | _V | ||||||||
| 3.5 | Creating bundles | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Splitters | __ | __ | _V | _V | _V | ||||||||
| 3.5 | Wire colors | _V | __ | _A | _V | _V | ||||||||
| 3.5 | Self-numbered labels | _V | __ | __ | _A | _A | ||||||||
| 3.5 | Placing components in a matrix | _V | __ | __ | _A | _A | ||||||||
| 3.5 | Combinational analysis | _V | __ | __ | __ | __ | ||||||||
| 3.5 | Opening Combinational Analysis | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Editing the truth table | _V | __ | CA | CA | CA | ||||||||
| 3.5 | Creating expressions | __ | __ | CA | CA | CA | ||||||||
| 3.5 | Generating a circuit | __ | __ | _V | _V | _V | ||||||||
| 3.5 | Import/Export Table | _V | __ | __ | __ | __ | ||||||||
| 3.5 | Menu reference | __ | __ | _A | __ | __ | ||||||||
| 3.5 | The File menu | _V | __ | _V | _V | _V | ||||||||
| 3.5 | The Edit menu | _V | __ | _V | _V | CV | ||||||||
| 3.5 | The Project menu | _C | _C | CA | _C | _C | Add VHDL | |||||||
| 3.5 | The Simulate menu | V | __ | CA | CV | CV | ||||||||
| FPGA Menu | ||||||||||||||
| 3.5 | The Window and Help menus | __ | __ | _A | __ | __ | ||||||||
| 3.5 | Export tab | _V | __ | _V | _V | _V | ||||||||
| 3.5 | Printing tab | _V | __ | _V | _V | _V | ||||||||
| 3.5 | Assembly viewer | __ | __ | __ | __ | __ | ||||||||
| 3.5 | Memory components | _V | __ | __ | __ | __ | ||||||||
| 3.5 | Poking memory | _V | __ | _A | _A | _A | ||||||||
| 3.5 | Hex editor | _V | __ | __ | _V | _V | ||||||||
| 3.5 | Pop-up menus and files | _V | __ | _V | _V | _V | ||||||||
| 3.5 | Memory file panel | _V | __ | __ | __ | __ | ||||||||
| 3.5 | v2.0 raw | _V | __ | __ | __ | __ | ||||||||
| 3.5 | v3.0 hex words | _V | __ | __ | __ | __ | ||||||||
| 3.5 | v3.0 hex bytes | _V | __ | __ | __ | __ | ||||||||
| 3.5 | Binary data | _V | __ | __ | __ | __ | ||||||||
| 3.5 | Ascii byte | _V | __ | __ | __ | __ | ||||||||
| 3.4 | Timing diagram | _V | __ | __ | __ | __ | ||||||||
| 3.4 | The Selection tab | _V | __ | __ | __ | __ | ||||||||
| 3.4 | The Timetable windows | _V | __ | __ | __ | __ | ||||||||
| 3.5 | Command-line verification | __ | __ | _T | __ | __ | ||||||||
| 3.5 | Substituting libraries | __ | __ | _T | __ | __ | ||||||||
| 3.5 | Other verification options | __ | __ | _T | __ | __ | ||||||||
| 3.5 | Testing multiple files | __ | __ | _T | __ | __ | ||||||||
| 3.5 | The Test Vector windows | _V | __ | _T | _T | _T | ||||||||
| 3.5 | Application preferences | CV | C_ | _T | C_ | C_ | ||||||||
| 3.5 | The Template tab | __ | __ | _T | __ | __ | ||||||||
| 3.5 | The International tab | C_ | C_ | CT | C_ | C_ | ||||||||
| 3.5 | The Window tab | _V | __ | _T | CV | CV | upd picture | |||||||
| 3.5 | The Layout tab | C_ | C_ | _T | CT | CT | Edit image/Delete Use a colorbind... | |||||||
| The Simulation tab | C_ | C_ | __ | __ | __ | |||||||||
| 3.5 | The Experimental tab | __ | __ | _T | __ | __ | ||||||||
| The Sofware tab | ||||||||||||||
| The FPGA tab | ||||||||||||||
| 3.5 | The command line | __ | __ | _V | _V | _V | ||||||||
| 3.5 | Project options | __ | __ | _T | __ | __ | ||||||||
| 3.5 | The Simulation tab | _V | __ | _T | _V | _V | ||||||||
| 3.5 | The Toolbar tab | __ | __ | _T | __ | __ | ||||||||
| 3.5 | The Mouse tab | __ | __ | _T | _V | _V | ||||||||
| 3.5 | Value propagation | _V | __ | _A | __ | __ | ||||||||
| 3.5 | Gate delays | __ | __ | _A | __ | __ | ||||||||
| 3.5 | Oscillation errors | __ | __ | _A | __ | __ | ||||||||
| 3.5 | Shortcomings | __ | __ | _A | __ | __ | ||||||||
| JAR libraries | __ | __ | __ | __ | __ | |||||||||
| Gray Code Incrementer | __ | _T | __ | __ | __ | |||||||||
| Library Class | __ | _T | __ | __ | __ | |||||||||
| Simple Gray Code Counter | __ | _T | __ | __ | __ | |||||||||
| Gray Code Counter | __ | _T | __ | __ | __ | |||||||||
| Guidelines | __ | _T | __ | __ | __ | |||||||||