----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:29:20 11/08/2018 
-- Design Name: 
-- Module Name:    topModule - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity topModule is
    Port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
           count_o : out  STD_LOGIC_VECTOR (3 downto 0));
end topModule;

architecture Behavioral of topModule is
	component prescaler is
	Generic( 
				width : integer := 8;
				value : integer := 255
			 );
    Port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
           enable_o : out  STD_LOGIC);
	end component;
	
	component counter is
	Generic( 
				width : integer := 8;
			 );
    Port ( clk_i : in  STD_LOGIC;
           rst_i : in  STD_LOGIC;
           enable_i : in  STD_LOGIC;
           count_o : out  STD_LOGIC_VECTOR (width downto 0));
	end component;

begin

	pr: prescaler
	generic map( 
				width => 27,
				value => 10000000
				)
	port map(
				clk_i => clk_i,
				rst_i => rst_i,
				enable_o => enable
				);

	-- connect the counter here
	
end Behavioral;