Sprotne naloge 5

1. Napišite zaporedje ukazov v zbirniku za procesor ARM, ki sešteje 32-bitni spremenljivki STEV1 in STEV2, rezultat pa zapiše v 32-bitno spremenljivko REZ. Nalogo ponovite še za primer, ko spremenljivko STEV2 odštejemo od spremenljivke STEV1. Naredite tudi različice za seštevanje in odštevanje 16-bitnih in 8-bitnih spremenljivk. STEV1 in STEV2 naj imata začetni vrednosti 10(10) in 5(10) zaporedoma, za REZ pa samo rezervirajte prostor.

2. Napišite zaporedje ukazov v zbirniku za procesor ARM, ki izračuna izraz STEV1=STEV2+STEV3–STEV1, pri čemer so STEV1, STEV2 in STEV3 32-bitne spremenljivke z začetnimi vrednostmi (določite jih s psevdoukazi): STEV1 = 50(16), STEV2 = 100(10), STEV3 = 2F(16).

3. Zapišite ukaz(e) v zbirniku za procesor ARM, ki v register naloži vrednost spremenljivke:
a) Nepredznačeno naloži 32-bitno vrednost 0x12345678 v register R1.
b) Nepredznačeno naloži 8-bitno vrednost 128 v register R2.
c) Predznačeno naloži 8-bitno vrednost 128 v register R3.
d) Nepredznačeno naloži 16-bitno vrednost 0xF123 v register R4.
e) Predznačeno naloži 16-bitno vrednost 0xF123 v register R5.

Vse primere rešite s posrednim naslavljanjem preko registra R0.

4. Napišite zaporedja ukazov v zbirniku za procesor ARM, ki izračunajo izraz STEV1=STEV1+STEV2 v primeru da:
a) Sta STEV1 in STEV2 8-bitni nepredznačeni spremenljivki z začetnima vrednostima 15(10) in 130(10).
b) Sta STEV1 in STEV2 8-bitni predznačeni spremenljivki z začetnima vrednostima 15(10) in 130(10).
c) Je STEV1 32-bitna spremenljivka, STEV2 pa 8-bitna predznačena spremenljivka. Začetni vrednosti sta: STEV1 = 128(10), STEV2 = 128(10).

Vse primere rešite s posrednim naslavljanjem preko registra R0.

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1. Write the sequence of instructions for the ARM processor, which sums the 32-bit STEV1 and STEV2 variables and writes the result to the 32-bit REZ variable. Repeat the task for the case when the STEV2 variable is subtracted from the STEV1 variable. Also make variations for adding and subtracting 16-bit and 8-bit variables. STEV1 and STEV2 should have initial values ​​10 (10) and 5 (10) in succession, and always only reserve the space for variable REZ.

2. Write the sequence of instructionss for the ARM processor, which calculates the expression STEV1 = STEV2 + STEV3-STEV1, where STEV1, STEV2, and STEV3 are 32-bit variables with initial values ​​(define them with pseudo-ininstructions): STEV1 = 50 (16) , STEV2 = 100 (10), STEV3 = 2F (16).

3. Write down the instructions(s) for the ARM processor that load the values in registers:

a) Unsigned load of 32-bit value 0x12345678 into register R1.

b) Unsigned load of  8-bit value 128 into the R2 register.

c) Signed load of  8-bit value 128 in the R3 register.

d) Unsigned load of 16-bit value of 0xF123 to the R4 register.

e) Signed load of 16-bit 0xF123 value in the R5 register.

Solve all cases by indirect addressing through the base register R0.

4. Write the sequence of instructions for the ARM processor that calculates the expression STEV1 = STEV1 + STEV2 if: 

a) STEV1 and STEV2 are 8-bit unsigned variables with initial values ​​of 15 (10) and 130 (10). 

b) STEV1 and STEV2 are 8-bit signed variables with initial values ​​of 15 (10) and 130 (10). 

c) STEV1 is a 32-bit variable and STEV2 is an 8-bit signed variable. Initial values ​​are: STEV1 = 128 (10), STEV2 = 128 (10). 

Solve all cases by indirect addressing through the base register R0.