rešitev - celota (od /* main program */ do konca)
Услови за завршување
/* main program */
_main:
/* user code here */
.equ PIOC_BASE, 0xFFFFF800 /* Zacetni naslov registrov za PIOC */
.equ PIO_PER, 0x00 /* Odmiki... */
.equ PIO_OER, 0x10
.equ PIO_SODR, 0x30
.equ PIO_CODR, 0x34
.equ PMC_BASE, 0xFFFFFC00 /* Power Management Controller */
/* Base Address */
.equ PMC_PCER, 0x10 /* Peripheral Clock Enable Register */
.equ TC0_BASE, 0xFFFA0000 /* TC0 Channel Base Address */
.equ TC_CCR, 0x00 /* TC0 Channel Control Register */
.equ TC_CMR, 0x04 /* TC0 Channel Mode Register*/
.equ TC_CV, 0x10 /* TC0 Counter Value */
.equ TC_RA, 0x14 /* TC0 Register A */
.equ TC_RB, 0x18 /* TC0 Register B */
.equ TC_RC, 0x1C /* TC0 Register C */
.equ TC_SR, 0x20 /* TC0 Status Register */
.equ TC_IER, 0x24 /* TC0 Interrupt Enable Register*/
.equ TC_IDR, 0x28 /* TC0 Interrupt Disable Register */
.equ TC_IMR, 0x2C /* TC0 Interrupt Mask Register */
.equ DBGU_BASE, 0xFFFFF200 /* Debug Unit Base Address */
.equ DBGU_CR, 0x00 /* DBGU Control Register */
.equ DBGU_MR, 0x04 /* DBGU Mode Register*/
.equ DBGU_IER, 0x08 /* DBGU Interrupt Enable Register*/
.equ DBGU_IDR, 0x0C /* DBGU Interrupt Disable Register */
.equ DBGU_IMR, 0x10 /* DBGU Interrupt Mask Register */
.equ DBGU_SR, 0x14 /* DBGU Status Register */
.equ DBGU_RHR, 0x18 /* DBGU Receive Holding Register */
.equ DBGU_THR, 0x1C /* DBGU Transmit Holding Register */
.equ DBGU_BRGR, 0x20 /* DBGU Baud Rate Generator Register */
.equ DBGU_RPR, 0x100 /* Receive Pointer Register */
.equ DBGU_RCR, 0x104 /* Receive Counter Register */
.equ DBGU_TPR, 0x108 /* Transmit Pointer Register */
.equ DBGU_TCR, 0x10C /* Transmit Counter Register */
.equ DBGU_RNPR, 0x110 /* Receive Next Pointer Register */
.equ DBGU_RNCR, 0x114 /* Receive Next Counter Register */
.equ DBGU_TNPR, 0x118 /* Transmit Next Pointer Register */
.equ DBGU_TNCR, 0x11C /* Transmit Next Counter Register */
.equ DBGU_PTCR, 0x120 /* Periph. Transfer Control Register */
.equ DBGU_PTSR, 0x124 /* Periph. Transfer Status Register */
bl INIT_IO
bl INIT_TC0
/* inicializacija debug unit-a */
bl DEBUG_INIT
zanka:
/* sproži sprejemanje preko DMA */
ldr r0, =niz1
ldr r1, =STRING_LENGTH
bl RCV_DMA
ldr r0,=DBGU_BASE
/* pocakaj na zastavico ENDRX */
z1: ldr r1, [r0, #DBGU_SR]
tst r1, #1 << 3
beq z1
/* zamenjaj velikost crk */
ldr r0, =niz1
ldr r1, =niz2
ldr r2, =STRING_LENGTH
bl CHANGE
/* sproži oddajanje preko DMA */
ldr r0, =niz2
ldr r1, =STRING_LENGTH
bl SND_DMA
/* pocakaj na zastavico ENDTX */
z2: ldr r1, [r0, #DBGU_SR]
tst r1, #1 << 4
beq z2
b zanka
_wait_for_ever:
b _wait_for_ever
RCV_DMA:
stmed r13!, {r2-r3,r14}
ldr r2,=DBGU_BASE
add r0,r0,#0x200000
str r0,[r2,#DBGU_RPR] /* kazalec na niz1*/
cmp r1, #1
movlo r1, #1
cmp r1, #80
movhi r1, #80
str r1,[r2,#DBGU_RCR]
mov r3,#1 /* omogoci sprejemanje - RXTEN*/
str r3,[r2,#DBGU_PTCR]
ldmed r13!, {r2-r3,pc}
SND_DMA:
stmed r13!, {r2-r3,r14}
ldr r2,=DBGU_BASE
add r0,r0,#0x200000
str r0,[r2,#DBGU_TPR] /* kazalec na niz1*/
str r1,[r2,#DBGU_TCR]
mov r3,#1<<8 /*omogoci oddajanje - TXTEN*/
str r3,[r2,#DBGU_PTCR]
ldmed r13!, {r2-r3,pc}
CHANGE:
stmed r13!, {r1-r4,r14}
ch_zanka:
ldrb r4, [r0], #1
bic r3, r4, #0b100000
cmp r3, #'A'
blo pisi
cmp r3, #'Z'
bhi pisi
eor r4, r4, #0b100000 /*veliko crko spremeni v majhno*/
pisi:
strb r4, [r1], #1 /* shranimo v niz2*/
subs r2, r2, #1
bne ch_zanka
ldmed r13!, {r1-r4,pc}
DEBUG_INIT:
stmfd r13!, {r0, r1, r14}
ldr r0, =DBGU_BASE
@ mov r1, #26 @ BR=115200
mov r1, #156 @ BR=19200
str r1, [r0, #DBGU_BRGR]
mov r1, #(1 << 11)
str r1, [r0, #DBGU_MR]
mov r1, #0b1010000
str r1, [r0, #DBGU_CR]
ldmfd r13!, {r0, r1, pc}
INIT_IO:
stmfd r13!, {r0, r2, r14}
ldr r2, =PIOC_BASE
mov r0, #1 << 1
str r0, [r2, #PIO_PER]
str r0, [r2, #PIO_OER]
ldmfd r13!, {r0, r2, pc}
INIT_TC0:
stmfd r13!, {r0, r2, r14}
ldr r2, =PMC_BASE @ korak 1.
mov r0, #1 << 17
str r0, [r2, #PMC_PCER]
ldr r2, =TC0_BASE @ korak 1.
mov r0, #0b110 << 13 @ korak 2.
add r0,r0,#0b011
str r0, [r2, #TC_CMR]
ldr r0,=375 @ korak 3.
str r0, [r2, #TC_RC]
mov r0, #0b101 @ korak 4.
str r0, [r2, #TC_CCR]
ldmfd r13!, {r0, r2, pc}
LED_ON:
stmfd r13!, {r0, r2, r14}
ldr r2, =PIOC_BASE
mov r0, #1 << 1
str r0, [r2, #PIO_CODR]
ldmfd r13!, {r0, r2, pc}
LED_OFF:
stmfd r13!, {r0, r2, r14}
ldr r2, =PIOC_BASE
mov r0, #1 << 1
str r0, [r2, #PIO_SODR]
ldmfd r13!, {r0, r2, pc}
DELAY:
stmfd r13!, {r1, r14}
MSEC: ldr r1,=48000
LOOP: subs r1,r1,#1
bne LOOP
subs r0,r0,#1
bne MSEC
ldmfd r13!, {r1, pc}
/* constants */
/* variables here */
.equ STRING_LENGTH, 6
niz1: .space STRING_LENGTH
niz2: .space STRING_LENGTH
/* variables end */
.align
_Lstack_end:
.long __STACK_END__
.end
_main:
/* user code here */
.equ PIOC_BASE, 0xFFFFF800 /* Zacetni naslov registrov za PIOC */
.equ PIO_PER, 0x00 /* Odmiki... */
.equ PIO_OER, 0x10
.equ PIO_SODR, 0x30
.equ PIO_CODR, 0x34
.equ PMC_BASE, 0xFFFFFC00 /* Power Management Controller */
/* Base Address */
.equ PMC_PCER, 0x10 /* Peripheral Clock Enable Register */
.equ TC0_BASE, 0xFFFA0000 /* TC0 Channel Base Address */
.equ TC_CCR, 0x00 /* TC0 Channel Control Register */
.equ TC_CMR, 0x04 /* TC0 Channel Mode Register*/
.equ TC_CV, 0x10 /* TC0 Counter Value */
.equ TC_RA, 0x14 /* TC0 Register A */
.equ TC_RB, 0x18 /* TC0 Register B */
.equ TC_RC, 0x1C /* TC0 Register C */
.equ TC_SR, 0x20 /* TC0 Status Register */
.equ TC_IER, 0x24 /* TC0 Interrupt Enable Register*/
.equ TC_IDR, 0x28 /* TC0 Interrupt Disable Register */
.equ TC_IMR, 0x2C /* TC0 Interrupt Mask Register */
.equ DBGU_BASE, 0xFFFFF200 /* Debug Unit Base Address */
.equ DBGU_CR, 0x00 /* DBGU Control Register */
.equ DBGU_MR, 0x04 /* DBGU Mode Register*/
.equ DBGU_IER, 0x08 /* DBGU Interrupt Enable Register*/
.equ DBGU_IDR, 0x0C /* DBGU Interrupt Disable Register */
.equ DBGU_IMR, 0x10 /* DBGU Interrupt Mask Register */
.equ DBGU_SR, 0x14 /* DBGU Status Register */
.equ DBGU_RHR, 0x18 /* DBGU Receive Holding Register */
.equ DBGU_THR, 0x1C /* DBGU Transmit Holding Register */
.equ DBGU_BRGR, 0x20 /* DBGU Baud Rate Generator Register */
.equ DBGU_RPR, 0x100 /* Receive Pointer Register */
.equ DBGU_RCR, 0x104 /* Receive Counter Register */
.equ DBGU_TPR, 0x108 /* Transmit Pointer Register */
.equ DBGU_TCR, 0x10C /* Transmit Counter Register */
.equ DBGU_RNPR, 0x110 /* Receive Next Pointer Register */
.equ DBGU_RNCR, 0x114 /* Receive Next Counter Register */
.equ DBGU_TNPR, 0x118 /* Transmit Next Pointer Register */
.equ DBGU_TNCR, 0x11C /* Transmit Next Counter Register */
.equ DBGU_PTCR, 0x120 /* Periph. Transfer Control Register */
.equ DBGU_PTSR, 0x124 /* Periph. Transfer Status Register */
bl INIT_IO
bl INIT_TC0
/* inicializacija debug unit-a */
bl DEBUG_INIT
zanka:
/* sproži sprejemanje preko DMA */
ldr r0, =niz1
ldr r1, =STRING_LENGTH
bl RCV_DMA
ldr r0,=DBGU_BASE
/* pocakaj na zastavico ENDRX */
z1: ldr r1, [r0, #DBGU_SR]
tst r1, #1 << 3
beq z1
/* zamenjaj velikost crk */
ldr r0, =niz1
ldr r1, =niz2
ldr r2, =STRING_LENGTH
bl CHANGE
/* sproži oddajanje preko DMA */
ldr r0, =niz2
ldr r1, =STRING_LENGTH
bl SND_DMA
/* pocakaj na zastavico ENDTX */
z2: ldr r1, [r0, #DBGU_SR]
tst r1, #1 << 4
beq z2
b zanka
_wait_for_ever:
b _wait_for_ever
RCV_DMA:
stmed r13!, {r2-r3,r14}
ldr r2,=DBGU_BASE
add r0,r0,#0x200000
str r0,[r2,#DBGU_RPR] /* kazalec na niz1*/
cmp r1, #1
movlo r1, #1
cmp r1, #80
movhi r1, #80
str r1,[r2,#DBGU_RCR]
mov r3,#1 /* omogoci sprejemanje - RXTEN*/
str r3,[r2,#DBGU_PTCR]
ldmed r13!, {r2-r3,pc}
SND_DMA:
stmed r13!, {r2-r3,r14}
ldr r2,=DBGU_BASE
add r0,r0,#0x200000
str r0,[r2,#DBGU_TPR] /* kazalec na niz1*/
str r1,[r2,#DBGU_TCR]
mov r3,#1<<8 /*omogoci oddajanje - TXTEN*/
str r3,[r2,#DBGU_PTCR]
ldmed r13!, {r2-r3,pc}
CHANGE:
stmed r13!, {r1-r4,r14}
ch_zanka:
ldrb r4, [r0], #1
bic r3, r4, #0b100000
cmp r3, #'A'
blo pisi
cmp r3, #'Z'
bhi pisi
eor r4, r4, #0b100000 /*veliko crko spremeni v majhno*/
pisi:
strb r4, [r1], #1 /* shranimo v niz2*/
subs r2, r2, #1
bne ch_zanka
ldmed r13!, {r1-r4,pc}
DEBUG_INIT:
stmfd r13!, {r0, r1, r14}
ldr r0, =DBGU_BASE
@ mov r1, #26 @ BR=115200
mov r1, #156 @ BR=19200
str r1, [r0, #DBGU_BRGR]
mov r1, #(1 << 11)
str r1, [r0, #DBGU_MR]
mov r1, #0b1010000
str r1, [r0, #DBGU_CR]
ldmfd r13!, {r0, r1, pc}
INIT_IO:
stmfd r13!, {r0, r2, r14}
ldr r2, =PIOC_BASE
mov r0, #1 << 1
str r0, [r2, #PIO_PER]
str r0, [r2, #PIO_OER]
ldmfd r13!, {r0, r2, pc}
INIT_TC0:
stmfd r13!, {r0, r2, r14}
ldr r2, =PMC_BASE @ korak 1.
mov r0, #1 << 17
str r0, [r2, #PMC_PCER]
ldr r2, =TC0_BASE @ korak 1.
mov r0, #0b110 << 13 @ korak 2.
add r0,r0,#0b011
str r0, [r2, #TC_CMR]
ldr r0,=375 @ korak 3.
str r0, [r2, #TC_RC]
mov r0, #0b101 @ korak 4.
str r0, [r2, #TC_CCR]
ldmfd r13!, {r0, r2, pc}
LED_ON:
stmfd r13!, {r0, r2, r14}
ldr r2, =PIOC_BASE
mov r0, #1 << 1
str r0, [r2, #PIO_CODR]
ldmfd r13!, {r0, r2, pc}
LED_OFF:
stmfd r13!, {r0, r2, r14}
ldr r2, =PIOC_BASE
mov r0, #1 << 1
str r0, [r2, #PIO_SODR]
ldmfd r13!, {r0, r2, pc}
DELAY:
stmfd r13!, {r1, r14}
MSEC: ldr r1,=48000
LOOP: subs r1,r1,#1
bne LOOP
subs r0,r0,#1
bne MSEC
ldmfd r13!, {r1, pc}
/* constants */
/* variables here */
.equ STRING_LENGTH, 6
niz1: .space STRING_LENGTH
niz2: .space STRING_LENGTH
/* variables end */
.align
_Lstack_end:
.long __STACK_END__
.end
Последна промена: среда, 4 јануари 2023, 13:51